This application relies for priority upon Korean Patent Application No. 2002-00452, filed on Jan. 4, 2002, the contents of which are herein incorporated by reference in their entirety.
The present invention relates to semiconductor devices and methods of fabricating the same and, more particularly, to semiconductor devices with capacitors of a metal-insulator-metal (MIM) structure (hereinafter inclusively referred as an MIM capacitor), and methods of fabricating the same.
In order to minimize the fabrication costs of semiconductor devices, it is preferred that the semiconductor devices be highly integrated and that the number of fabricating steps be reduced. As portable electronic devices such as cellular telephones, camcorders, and electronic game machines have increased in popularity, there has evolved a heightened need for embedded memory logic (EML) semiconductor devices that include both memory and logic circuits. Such EML semiconductor devices generally employ DRAMs as memories for high-speed operations.
FIG. 1 is a cross-sectional view for illustrating a method of fabricating a capacitor of a typical DRAM semiconductor device.
Referring to FIG. 1, a first interlayer dielectric layer (ILD) is formed on the semiconductor device 10. Thereafter, the first ILD is patterned to form a first interlayer dielectric layer pattern (ILD pattern) 20 with a first opening 25 exposing the semiconductor device 10. A conductive contact plug 30 is formed through the first opening 25 to be connected to the semiconductor substrate 10. At this time, the first ILD pattern 20 covers a gate pattern (not shown) formed on the semiconductor substrate.
A second ILD is formed on an entire surface of the semiconductor substrate including the contact plug 30. Thereafter, the second ILD is patterned to form a second ILD 40 with a second opening 45 exposing a top surface of the contact plug 30.
A lower electrode layer and a sacrificial layer (not shown) are conformally formed on an entire surface of the semiconductor substrate including the second ILD pattern 40. Next, the sacrificial layer and the lower electrode layer are etched to expose a top surface of the second ILD pattern 40, thereby forming a lower electrode 50 and a sacrificial layer pattern, which sequentially fill the second opening 45. The sacrificial layer pattern is then removed to expose an inner wall of the lower electrode 50.
A dielectric layer 60 and an upper electrode layer are sequentially formed on an entire surface of the semiconductor substrate including the exposed lower electrode 50. The upper electrode layer is patterned to expose a top surface of the dielectric layer 60, thereby forming an upper electrode 70, which fills the second opening 45 and crosses thereon.
Fabrication of a DRAM capacitor according to the foregoing conventional method comprises performing the photolithographic and etching processes three times in order to form the first opening 25, the second opening 45, and the upper electrode 70.
In addition, as shown in FIG. 1, a DRAM cell capacitor typically includes a lower electrode having a height h1 of about 10000 xc3x85 and higher, so as to enable high integration and to secure a sufficient capacitance value. However, because the height h1 of the lower electrode 50 is relatively high, fabricating processes of DRAMs are incompatible with those of logic circuits. In addition, a higher voltage may be applied to the capacitors for logic circuits than the capacitors for memories. Thus, the capacitors for the logic circuits generally include thicker capacitor dielectric layers so as to have a sufficient breakdown voltage as compared with the capacitors for the memories. As a result, the capacitors for logic circuits are fabricated to have a different thickness through different process steps than that of the capacitors of memories, complicating production, and therefore leading to higher fabrication costs.
It is therefore a feature of the present invention to provide semiconductor devices with capacitors for logic circuits and capacitors for DRAMs, having structures that are similar to each other, so as to be suitable for fabricating EML semiconductor devices.
It is another feature of the present invention to provide methods of fabricating capacitors of semiconductor devices, which are suitable for EML semiconductor devices and which can reduce fabrication costs.
In this manner, a capacitor structure and method are provided for decreasing the number of the photolithographic and etching processes to realize process simplification and reduce associated costs in the fabrication of semiconductor device capacitors.
In accordance with a feature of the present invention, provided is a capacitor of a semiconductor device in which capacitors for logic circuits and capacitors for DRAMs are disposed in an interlayer dielectric layer (ILD) covering gate patterns. The capacitor includes an interlayer dielectric layer pattern (ILD pattern) that is disposed over a semiconductor substrate including a memory region and a logic circuit region, and has first and second openings exposing the semiconductor substrate of the memory and logic circuit regions, respectively. A sidewall and a bottom of the first opening are covered with a first lower electrode, and a sidewall and a bottom of the second opening are covered with a second lower electrode. Inner walls of the first and second lower electrodes are covered with an upper dielectric layer. The upper dielectric layer is covered with first and second upper electrodes at the first and second openings, respectively. A lower dielectric layer pattern is intervened between the second lower electrode and the upper dielectric layer.
Preferably, the lower dielectric layer pattern and the upper dielectric layer are formed of at least one material selected from the group consisting of a tantalum oxide layer (Ta2O5), an aluminum oxide layer (Al2O3), a titanium oxide layer (TiO2), a silicon oxide layer (SiO2), a silicon nitride layer (Si3N4), and a hafnium oxide layer (HfO2).
In addition, the first and second upper electrodes are preferably composed of at least one material selected from the group consisting of titanium nitride, titanium, cobalt, tungsten, and ruthenium. Likewise, the first and second lower electrodes are preferably composed of at least one material selected from the group consisting of titanium nitride, titanium, cobalt, tungsten, tungsten, and ruthenium.
It is preferable that a heavily doped region is additionally disposed in the semiconductor substrate under the first and second openings.
In accordance with another feature of the present invention, provided is a method of fabricating a capacitor of a semiconductor device comprising selectively removing a lower dielectric layer formed in a memory region. The method comprises forming an ILD on a semiconductor substrate including memory and logic circuit regions and patterning the resultant structure. As a result, an ILD pattern is formed to have first and second openings exposing the semiconductor substrate of the memory and logic circuit regions, respectively. Thereafter, first and second lower electrodes are formed in the first and second openings, respectively. After forming a lower dielectric layer pattern covering the second lower electrode, an upper dielectric layer and an upper electrode are sequentially formed on an entire surface of the resultant structure.
Preferably, before forming the ILD, a heavily doped region is formed in the semiconductor substrate under the first and second openings.
The first and second lower electrodes are preferably composed of at least one selected from the group consisting of titanium nitride, titanium, cobalt, tungsten, and ruthenium.
Forming the first and second lower electrodes comprises sequentially stacking a lower electrode layer and a sacrificial layer on an entire surface of the semiconductor substrate where the first and second openings are formed, successively etching the sacrificial layer and the lower electrode layer to expose a top surface of the ILD pattern, and removing the sacrificial layer. In this case, the sacrificial layer is preferably composed of at least one material selected from SOG materials and photoresist materials. The sacrificial layer is preferably removed by a wet etch process using an etch recipe having an etch selectivity with respect to the ILD, and first and second lower electrodes.
Forming the lower dielectric layer pattern comprises conformally forming a lower dielectric layer on an entire surface of the semiconductor substrate where the first and second lower electrodes are formed, forming a mask pattern covering the lower dielectric layer disposed on the second lower electrode, and removing the lower dielectric layer covering the first lower electrode by using the mask pattern as an etch mask. Preferably, the lower dielectric layer covering the first lower electrode is removed by an isotropic etch process using an etch recipe having an etch selectivity with respect to the first lower electrode and the ILD pattern.
The lower dielectric layer pattern preferably comprises at least one material selected from the group consisting of a tantalum oxide layer (Ta2O5), an aluminum oxide layer (Al2O3), a titanium oxide layer (TiO2), a silicon oxide layer (SiO2), a silicon nitride layer (Si3N4), and a hafnium oxide layer (HfO2).
Likewise, the upper dielectric layer is preferably at least one material selected from the group consisting of a tantalum oxide layer (Ta2O5), an aluminum oxide layer (Al2O3), a titanium oxide layer (TiO2), a silicon oxide layer (SiO2), a silicon nitride layer (Si3N4), and a hafnium oxide layer (HfO2).
The upper electrode layer preferably comprises a material selected from the group consisting of titanium nitride, titanium, cobalt, tungsten, and ruthenium.
After forming the upper electrode layer, the upper electrode layer is preferably patterned to form first and second upper electrodes that cross the first and second openings, respectively.